View ZL40510LDG_4561419.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. features ? single 5 v supply (10%) ? 150 ma low-noise read channel with 100 x current gain ? three 500 ma write channels with 240 x gain ? combined channel output 700 ma ? dual output for dvd/cd laser ? rise and fall times 1 ns typical ? oscillator, 500 mhz, 100 ma with external resistor control of frequency and amplitude ? power up/down control ? lvds control signals ? > 2 kv esd ?low r th qfn package ? contact zarlink for available custom gain and input impedance options applications ?dvdrw/ram ?dvdr ?cd-rw ?cd-r ? write optical drives ? laser diode current switch ? supports double density dvd august 2006 ordering information zl40510lde 24 pin qfn tubes, bake & drypack zl40510ldf 24 pin qfn tape & reel ZL40510LDG 24 pin qfn trays, bake & drypack zl40514lde 24 pin qfn tubes, bake & drypack zl40514ldf 24 pin qfn tape & reel zl40514ldg 24 pin qfn trays, bake & drypack -40 c to +85 c zl40510/14 dual output dvd and cd 4 channel laser diode drivers data sheet figure 1 - functional block diagram 19 20 gnd 21 gnd 22 gnd pwr_up inr in2 in3 in4 gnd_in 23 gnd 1 en2 /en2 24 2 3 en3 /en3 4 5 en4 /en4 6 vcc_in 7 oscen 8 rfa rfb rsa rsb sela vcc_a outa gnd outb vcc_b 18 17 16 15 14 13 12 11 10 9
zl40510/14 data sheet 2 zarlink semiconductor inc. figure 2 - pinout of 4x4 mm 24 pin qfn (top view) description the zl40510/14 are high performance la ser drivers capable of driving two separate cathode grounded laser diodes (e.g., 650 nm and 780 nm laser diodes). the zl40510/14 contain a 150 ma low-noise read channel (chr), and three 500 ma write channels (ch2, ch3 and ch4). the read channel amplifies the posi tive current supplied at its reference input, inr, by a fixed factor of 100. write channels amplify the positive currents supplied at its reference inputs in2, in3, and in4 by a fixed factor of 240. an on-chip rf oscillator is provided for the reduction of laser mode hopping noise. the zl40510 offers higher tolerance performance. 24 23 22 13 14 1 2 3 4 5 6 21 20 19 18 17 16 15 zl40510 vcc_a vcc_b gnd outa outb sela 9 10 11 12 8 7 /en4 en4 /en3 en3 /en2 en2 pwr_up gnd_in in4 in3 in2 inr vcc_in oscen rfa rfb rsa rsb
zl40510/14 data sheet table of contents 3 zarlink semiconductor inc. 1.0 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 read and write channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 on-chip rf oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 electrical and optical pulse response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 specified electrical performance with 15 mm interconnect and za rlink zle40510/14 evaluation board. . 7 1.6 application layout guide lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.7 zle40510/14 interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 evaluation boards from zarlink semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 optical pulse response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.0 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.0 characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.0 i/o diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.0 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 example waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 write waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 oscillator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
zl40510/14 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pinout of 4x4 mm 24 pin qfn (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - pulse response model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4 - zle40510/14 application board electrical interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5 - application schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6 - typical optical eye diagram response* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7 - write channel 2, 3 and 4 ip/op transfer characteristic/temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 - read channel ip/op transfer characteristic/temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 - write channel 2, 3 or 4 ip/op transfer characteristic/vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 - write channel 2, 3 or 4 ip/op best fit line% error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 - write channel 2, 3 or 4 ? lout% variation with temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 - write channel 2, 3 or 4 ? lout% variation with vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13 - oscillator frequency/rf vcc = 5 v, temp = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14 - losc out/frequency/ rs = 1 k, 7.5 k, 11 k, vcc = 5 v, temp = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15 - losc amplitude ma pk-pk/rsa or rsb vcc = 5 v, temp = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16 - losc/frequency rs = 7.5 k, vcc = 5 v, temp = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17 - ? freq% variation with temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18 - oscillator noise spectral density vcc = 5 v, temp = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19 - cmos/lvttl input (pwr_up, oscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20 - oscillator resistors (rf, rs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21 - read current input (inr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22 - output (outa, outb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23 - write current input (in2, in3, in4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24 - lvds input (en2, /en2), (en3, /en3), (en4, /en4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25 - timing of read or write channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 26 - output waveform showing addition of read and write levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 27 - example of write waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 28 - example of oscillator waveform superimposed on the read waveform . . . . . . . . . . . . . . . . . . . . . . 28
zl40510/14 data sheet 5 zarlink semiconductor inc. 1.0 application notes 1.1 read and write channel operation the read channel is activated by applyi ng a 'high' signal to the pwr_up pin. in this mode, the fast write channels can be enabled by applying a 'high' signal to the respective pair of write enable pins (en2, /en2), (en3, /en3) or (en4, /en4). the output currents of the four channel s are summed together and output as a composite signal at either outa (if sela select is 'high') or outb (if sela select is 'low'). this provides the ability to drive two different laser diodes with just one zl40510/14. voltage control of the channel reference inputs (inr, in 2, in3 and in4) can be achieved quite easily using an external resistor r ref in series with the reference channel inpu t to convert a given reference potential v ref to an input current, i in : where r in is the input impedance of the respective reference channel. 1.2 on-chip rf oscillator an on-chip rf oscillator is enabled if oscen = 'high', and its output signal is added to the appropriate current output (outa, if sela select is 'high' , or outb, if sela select is 'low'). the oscillator amplitude is set by an external resistor from rsa or rsb to gnd. its frequency is set by an external resistor rfa or rfb to gnd. rsa and rfa are selected when sela is ?high?. the oscillator signal is summed with the programmed write and read levels before amplification to the output. the oscillator signal has zero dc level and +i_pk to ?i_pk signal swing. consequently, if the programmed dc level from the write and read channels is less than the pk level pr ogrammed for the oscillator, the combined signal will be clipped on the negative cy cle of the signal. this will increase the harmonic content of t he output signal and reduce the pk to pk amplitude output. 1.3 thermal considerations package thermal resistance is 40 c/w under the eia/jesd51-3 comp liant pcb test board condition. users should ensure that the junction temperature does not exceed 150 c. thermal resistance from junction to case and to ambient is very much dependent on how the ic is mounted onto the board, on the pcb layout and on any heat extraction arrangements. power consumption and system ambient operating temper ature limits should be noted and careful thermal gradient calculations undertaken to ensure that the junction temperatur e never exceeds 150 c. in ref ref in r r v i + = ,
zl40510/14 data sheet 6 zarlink semiconductor inc. 1.4 electrical and optical pulse response figure 3 - pulse response model figure 3 illustrates a simplified model of the typical zl40510/14 a nd the application. the zl40510/14 consists of an ideal switched current source and an equivalent model of the zl40510/14 output stage. the electrical model for the laser diode is a voltage source vd (v_on) in series with the on resistance rd all in parallel with the junction capacitance cd. this simplified model approximately re presents the laser diode elec trical load when operated beyond the laser threshold. to a firs t approximation, the optical output is pr oportional to the current flow in the resistor rd. the laser diode and the zl40510/14 are connected together by interconnect tracks with the return current passing through the supply decoupling bypass capacitor between ground and output vcc. the zl40510/14 can be approximated to an ideal switched programmed current source with a propagation delay of iout_on (1.2 ns) and a switch transition time of 400 ps. the final output electrical pulse response parameters, trise, tfall, overshoot and undershoot are determined by the co mbined electrical network as illustrated in figure 3. for example, the rise time and fall time for large current steps can be slew rate limited by the combined interconnect and fixed interconnect inductance. the fixe d inductance represents that associated with packaging and minimum interconnect distance. the interconnect induct ance is that associated with the additional tracking between laser diode and the zl40510/14 to accommodate application physical limitations. for example, if a pulse of 360 ma amplitude (40 ma to 400 ma) is to be switched in a time of 1 ns with the vd = 1.6 v, then the maximum volt drop across the interconnec t inductance is approximately 3.5 v (maximum vpin for 500 ma output) ? 1.6 v (vdiode) = 1.9 v. consequently, l* di/dt < 1.9 v. hence, l < 1.9/ (0.36a/1 ns) = 5.3 nh. small current step size rise and fall time will be determined by the bandw idth of the combined network. this is dominated by the interconnect inductance and the output capacitance. similarly, t he overshoot and undershoot will be determined by the q of the network. this is a fu nction of the source impedanc e from the zl40510/14, the interconnect inductance and the load impedance of the laser diode. figure 3 in cludes example simplified estimates of the q and bw of the combined laser di ode, zl40510/14 and interconnect network for two different interconnect inductance values (5 nh and 7 nh) and two different diode on resistance (3 ohm and 7 ohm). this simple analysis illustra tes the change in bw and q of the network depending on these parameters . this in turn effects the rise time and fall time and the overshoot a nd undershoot performance ac hieved in the application. en iout 500 17p 15 2p zl40510 model vd rd cd lint c_out lfix = 3nh lint=5nh , bw = 460mhz, rd=7, q=j20/(15+7) =0.9 lint=5nh, bw = 460mhz, rd=3, q=j20/(15+3) = 1.11 lint=7nh, bw = 411mhz, rd=7, q=j18/(15+7) = 0.8 lint=7nh, bw = 411mhz, rd=3, q=j18/(15+3) = 1.0 lint lfix = 3nh c_bypass k k vcc_a outa
zl40510/14 data sheet 7 zarlink semiconductor inc. 1.5 specified electrical performance with 15 mm interconnect and zarlink zle40510/14 evaluation board the specified performance in the table are results based on the electrical measurements and simulations across full process corners using the zarlink evaluation board using a 3.9 ohm resistive load to ground. the track interconnect between zl40510/14 and the 3.9 ohm resistor is 15 mm long and uses a 2 mm wide track on single sided fr4 board. the return path is via two 2 mm wide tracks spaced 0.25 mm either side of the track between output and the 3.9 ohm resistor. the combined forw ard and return path forms a co planar transmission line with a characteristic impeda nce of approximately 120 ohms. the tight coupled return paths carrying the return current reduce the effective series inductance (leff) which can be approximated to: leff = 2 * lint * (1 - k) + 2 * lfix * (1 - k). the zle40510 board has two positions for the laser diode at two different distances. (15 and 30 mm). ? the measured value of leff is 7 nh ? the estimated value of leff = 2 * 8 (1 ? 0.5) = 8 nh the actual pulse response achieved in an app lication is thus dependent on the application. 1.6 application layout guide lines minimize interconnect inductance by: a. using short interconnect distance b. use wide interconnect tracks c. keep the return path tightly coupled to the forward path.
zl40510/14 data sheet 8 zarlink semiconductor inc. 1.7 zle40510/14 interconnect figure 4 - zle40510/14 application board electrical interconnect
zl40510/14 data sheet 9 zarlink semiconductor inc. 2.0 application diagram figure 5 - application schematic diagram 3.0 evaluation boards from zarlink semiconductor zarlink semiconductor provides an ldd evaluation board. th is is primarily for those interested in performing their own assessment of the operation of the ldds. figure 5 shows a recommended applic ation configuration. the inputs are connected via side launch sma connectors. please order as zle40510. 24 23 22 13 14 1 2 3 4 5 6 21 20 19 18 17 16 15 zl40510 vcc_a vcc_b gnd outa outb sela 9 10 11 12 8 7 /en4 en4 /en3 en3 /en2 en2 pwr_up gnd_in in4 in3 in2 inr vcc_in oscen rfa rfb rsa rsb vcc 470uf 470nf 470nf gnd 750r 750r 620r 10k 1nf 750r 12k 6k2 750r 12k 50r 4r7 gnd 1nf
zl40510/14 data sheet 10 zarlink semiconductor inc. 4.0 optical pulse response figure 6 - typical optical eye diagram response* * (measured using sanyo dl-7140-201s infra red laser mounted on zle40510 application board) (i read = 50 ma, i write =125 ma, at 15 mm with 200 mhz prbs pattern) figure 6 illustrates the typical optical response me asured with the zl40510/14 mounted on the zle40510/14 application board driving a sanyo dl-7140-201s infra red laser. the test condition is driving a prbs pattern at 200 mhz clock rate which is representative of a 16x dv d write pattern using block write strategy with minimum write pulse of 2t duration. the sanyo dl-7140-201s infra red laser diode on resistance is typically 3 ohms which is representative of the on resistance of the latest generation 250 mw pulsed hi gh power red laser diodes that are targeted at 16x and 8x dvd. the pulse is measured stepping from a low level which is above the laser threshold thus avoiding the laser turn on transient which can distort the measured response. the zl40510/14 exhibits excellent pulse response char acteristics when used with the optimum interconnect. 5ns
zl40510/14 data sheet 11 zarlink semiconductor inc. 5.0 pin list pin no. pin name type function 1 en2 lvds positive digital control input for channel 2 2 /en2 lvds negative digital contro l input for channel 2 3 en3 lvds positive digital control input for channel 3 4 /en3 lvds negative digital contro l input for channel 3 5 en4 lvds positive digital control input for channel 4 6 /en4 lvds negative digital contro l input for channel 4 7 vcc_in supply +5 v input power supply 8 oscen digital oscillator enable control input, high active (ttl) 9 rfa analog resistor to gnd sets oscill ator frequency when sela = ?high? 10 rfb analog resistor to gnd sets oscill ator frequency when sela = ?low? 11 rsa analog resistor to gnd sets oscillat or amplitude when sela = ?high? 12 rsb analog resistor to gnd sets oscillat or amplitude when sela = ?low? 13 sela digital output select input; 'high' selects outa, 'low' selects outb (ttl) 14 vcc_b supply output b vcc 15 outb analog current output source b 16 gnd supply ground 17 outa analog current output source a 18 vcc_a supply output a vcc 19 pwr_up digital digital chip enable control input, high active (cmos) 20 inr analog current input, r in = 400 ohms to gnd 21 in2 analog current input, r in = 250 ohms to gnd (optional 500 ohms) 22 in3 analog current input, r in = 250 ohms to gnd (optional 500 ohms) 23 in4 analog current input, r in = 250 ohms to gnd (optional 500 ohms) 24 gnd_in supply ground for input circuit
zl40510/14 data sheet 12 zarlink semiconductor inc. absolute maximum ratings characteristic min. typ. max. units comments supply voltage (vcc, vcc_in) -0.5 6.0 v input voltage (inr, in2, in3, in4) -0.5 6.0 v input voltage (pwr_up, en2, /en2, en3, /en3, en4, /en4, oscen, sela) -0.5 (vcc_i n + 0.5) v output voltage (outa, outb) -0.5 vcc v junction temperature 150 c operating range characteristic min. typ. max. units comments supply voltage (vcc, vcc_in) 4.5 5.5 v input voltage (inr) 0.7 v input voltage (in2, in3, in4) 0.7 v output voltage (outa, outb) -0.3 (vcca, b-0.9) v rf 1 k ? external resistor to gnd rs 1 k ? external resistor to gnd operating temperature range, junction 0 150 c package thermal resistance package type junction to units comments case r thjc ambient r thja 24 pin qfn 40 k/w exposed paddle soldered to multi-layer pcb
zl40510/14 data sheet 13 zarlink semiconductor inc. note: a = 100% tested b = guaranteed by characterization and design c = guaranteed by simulation electrical characteristics vcc = 5 v, t amb = 25c, inr = 400 a, in2 = in3 = in4 = 160 a, pwr_up = high, ch2, ch3, ch4 disabled, oscen = low, unless otherwise specified. characteristic min. typ. max. units comments type supply current (into vcc-pin) supply current, power down, i ccpd 80 220 a enable = low a supply current, read mode, oscillator disabled, i ccr0 69 84 ma inr = 400 aa supply current, read mode, oscillator enabled, i ccr1 70 85 ma oscen = high, rf = 6.8 kohm, rs = 8.2 kohm, a supply current, write mode, i ccw 210 250 ma ch2, ch3, ch4 enabled b supply current, input off 1 8 ma ch2, ch3, ch4 enabled inr = in2 = in3 = in4 = 0 b sela & oscen digital inputs logic low voltage 0.8 v a logic high voltage 2.2 v a threshold level 1.68 v temperature stabilised b logic low input current -50 av in = 0 v b logic high input current 50 av in = 3.3 v b power_up digital input logic low voltage 0.5 v cmos compatible level a logic high voltage 2.7 v cmos compatible level a logic low input current -50 av in = 0 v b logic high input current 50 av in = 3.3 v b lvds digital inputs input voltage range 0 2.4 v b differential input voltage 100 600 mv v(en2~/en2) lvds compatible v(en3~/en3) lvds compatible v(en4~/en4) lvds compatible a differential input impedance 87 110 133 ? b common mode input impedance 10 k ? internal resistor to vcc b
zl40510/14 data sheet 14 zarlink semiconductor inc. characteristic min. typ. max. units comments type current outputs (outa & outb) output current, chr 150 200 ma v out 3.5 v b output current, ch2, ch3, ch4 500 ma channel enabled, inr = 0 a, v out 3.5 v,iin = 2.8 ma a total output current 700 ma ch2, 3, 4 enabled, v out 3.5 v a write output current, zero input, i out0 (zl40510) 12 ma inr = in2 = in3 = in4 = 0 a, ch2, or ch3 or ch4 enabled a write output current, zero input, i out0 (zl40514) 15 ma inr = in2 = in3 = in4 = 0 a, ch2, or ch3 or ch4 enabled read output current, zero input, i out0 2.5 ma inr = in2 = in3 = in4 = 0 a, ch2, 3 & 4 disabled a input impedance (inr) 330 400 470 ? r in is to gnd b input impedance (in2, in3, in4) 205 250 295 ? r in is to gnd b i out supply sensitivity (any channel) -5 +5 %/v i out = 40 ma to 300 ma b i out temperature sensitivity (any channel) 300 ppm/ c i out = 40 ma to 300 ma, i in temp coefficient = 0 ppm/c b i out current output noise 3 na/ hz i out = 50 ma inr = 500 ua b current output outa & outb current gain, chr, best fit 85 100 115 ma/m a i out = 20 ma to 80 ma ?note 1 a current gain, ch2, best fit 205 240 275 ma/m a i out = 20 ma to 120 ma ? note 2 a current gain, ch3, best fit 205 240 275 ma/m a i out = 20 ma to 120 ma ? note 2 a current gain, ch4, best fit 205 240 275 ma/m a i out = 20 ma to 120 ma ? note 2 a zl40510 output current offset, chr, best fit. -1 8 ma i out = 20 ma to 80 ma ? note 1 a output current offset, ch2, best fit -4 12 ma i out = 20 ma to 120 ma ? note 2 a output current offset, ch3, best fit -4 12 ma i out = 20 ma to 120 ma ? note 2 a
zl40510/14 data sheet 15 zarlink semiconductor inc. note: a = 100% tested b = guaranteed by characterization and design c= guaranteed by design note 1: gain, offset and linearity of a channel are derived from a best fit line (linear regression graph) to the following thre e operating points: iout = 20ma, 50ma and 80ma. note 2: gain, offset and linearity of a channel are derived from a best fit line (linear regression graph) to the following thre e operating points: iout = 20ma, 70ma and 120ma. note 3: best fit output line through 20ma,50ma,80ma note 4: best fit output line through 20ma,70ma,120ma ? electrical measurement into 3.9 ohm to gnd output current offset, ch4, best fit -4 12 ma i out = 20 ma to 120 ma ? note 2 a zl40514 output current offset, chr, best fit. note 3 -1 8 ma i out = 20 ma to 80 ma ? note 1 a output current offset, ch2, best fit. note 4 -7 15 ma i out = 20 ma to 120 ma ? note 2 a output current offset, ch3, best fit. note 4 -7 15 ma i out = 20 ma to 120 ma ? note 2 a output current offset, ch4, best fit. note 4 -7 15 ma i out = 20 ma to 120 ma ? note 2 a zl40510 & zl40514 output current linearity (any channel). note 3 -3.5 1.5 % i out = 20 ma to 120 ma ? note 2 a gain tracking, ch2 to ch3 to ch4 -2.5 +2.5 % i out = 20 ma to 120 ma ? note 2 a characteristic min. typ. max. units comments type
zl40510/14 data sheet 16 zarlink semiconductor inc. note: a = 100% tested b = guaranteed by characterization and design c= guaranteed by design ? (en2, /en2), (en3, /en3), (en4, /en4) input pulse rise and fall time = 0.4 ns. ? parameter is measured electrical pulse response using 3.9 ohm load to gnd and zarlink application board. pulse response perform ance parameters trise, tfall, overshoot and unde rshoot can be limited by inte rconnect inductance. optical response is influenced by laser diode response. see application notes. characteristic min. typ. max. units comments type timing current output outa & outb channel rise time, (10% to 90%), t r2 0.9 1.2 ns 40 to 375 ma, ch2, 3 or 4 pulsed ? ? b channel fall time, (10% to 90%), t f2 1.1 1.4 ns 40 to 375 ma, ch2, 3 or 4 pulsed ? ? b output current overshoot (any write channel) 13 % 40 to 375 ma ch2 3, 4 pulsed ? b output current undershoot (any write channel) 13 % 40 to 375 ma ch2 3, 4 pulsed ? b channel to channel enable skew tr 50 ps b channel to channel enable skew tf 25 ps b i out on propagation delay, t onch 1.4 1.8 ns 50% en high-low to 50% i out , any write channel b i out off propagation delay, t offch 1.2 1.6 ns 50% en low-high to 50% i out , any write channel b amplifier -3db bandwidth (chr) 23 43 68 mhz inr = 400 ac amplifier -3db bandwidth (ch2, 3, 4) 6 11 16 mhz in2, in3, in4 = 400 ac power_up & sela power_up time, t on 1.5 3.5 s 50% enable low-high to 50% i out c power_up time, t off 20 33 ns 50% enable high-low to 50% i out c output a select delay 5 8 ns 50% dvd/cd select low-high to 50% i outa c output a deselect delay 5 8 ns 50% dvd/cd select high-low to 50% i outa c
zl40510/14 data sheet 17 zarlink semiconductor inc. note: a = 100% tested b = guaranteed by characterization and design c= guaranteed by design ? (en2, /en2), (en3, /en3), (en4, /e n4) pulse rise and fall time = 0.4 ns. electrical dynami c characteristics vcc = 5 v, t amb = 25c, inr = 400 ua, in2 = in3 = in4 = 160 a, pwr_up = high, ch2, ch3, ch4 disabled, oscen = low, unless otherwise specified. characteristic min. typ. max. units comments type oscillator frequency adjust range low 250 mhz rf = 16 k ? , oscen = high b frequency adjust range high 575 mhz rf = 2 k ? , oscen = high b frequency tolerance (zl40510) 338 375 412 mhz rf = 7.5 k ? , oscen = high a frequency tolerance (zl40514) 322 375 428 mhz rf = 7.5 k ? , oscen = high a frequency temperature coefficient 200 ppm/ c rf = 7.5 k ? , oscen = high c amplitude adjust range low (rs=11k ? ) 36 ma pk to pk rs = 11 k ? , oscen = high rf=9 k (350 mhz) inr = 1 ma b amplitude adjust range high (rs=1k ? ) 100 ma pk to pk rs = 1 k ? , oscen = high rf = 9 k (330 mhz) inr = 1 ma b third harmonic -30 dbc rs = 10 k ? to 2 k ? , oscen = high rf = 9 k (330 mhz) inr = 400 ua c second harmonic -20 dbc rs = 10 k ? to 2 k ? , oscen = high rf = 9 k (330 mhz) inr = 400 ua c amplitude tolerance -20 0 20 % fosc= 250 mhz to 450 mhz, oscen = high, rs 1% c amplitude (rs = 7.5 k) 42 ma pk to pk f = 375 mhz, rs = 7.5 k ? , oscen = high c amplitude flatness 4dbrs = 7.5k ? , rf = 9 k ? to 4 k ? b amplitude temperature coefficient 800 ppm/ c rf = 5.6 k ? , oscen = high c oscillator enable time, t onosc 2 ns 50% oscen high-low to 50% i out b oscillator disable time, t offosc 3 ns 50% oscen low-high to 50% i out b
zl40510/14 data sheet 18 zarlink semiconductor inc. 6.0 characteristic curves figure 7 - write channel 2, 3 and 4 ip/op transfer characteristic/temp figure 8 - read channel ip/op transfer characteristic/temp
zl40510/14 data sheet 19 zarlink semiconductor inc. figure 9 - write channel 2, 3 or 4 ip/op transfer characteristic/vcc figure 10 - write channel 2, 3 or 4 ip/op best fit line% error
zl40510/14 data sheet 20 zarlink semiconductor inc. figure 11 - write channel 2, 3 or 4 ? lout% variation with temperature figure 12 - write channel 2, 3 or 4 ? lout% variation with vcc
zl40510/14 data sheet 21 zarlink semiconductor inc. figure 13 - oscillator frequency/rf vcc = 5 v, temp = 25 c figure 14 - losc out/frequency/ rs = 1 k, 7.5 k, 11 k, vcc = 5 v, temp = 25 c
zl40510/14 data sheet 22 zarlink semiconductor inc. figure 15 - losc amplitude ma pk-pk/rsa or rsb vcc = 5 v, temp = 25 c figure 16 - losc/frequency rs = 7.5 k, vcc = 5 v, temp = 25 c
zl40510/14 data sheet 23 zarlink semiconductor inc. figure 17 - ? freq% variation with temperature figure 18 - oscillator noise spectral density vcc = 5 v, temp = 25 c
zl40510/14 data sheet 24 zarlink semiconductor inc. 7.0 i/o diagrams figure 19 - cmos/lvttl input (pwr_up, oscen) figure 20 - oscillator resistors (rf, rs) figure 21 - read current input (inr) vcc 300k vcc vref vcc 400r
zl40510/14 data sheet 25 zarlink semiconductor inc. figure 22 - output (outa, outb) figure 23 - write current input (in2, in3, in4) figure 24 - lvds input (en2, / en2), (en3, /en3), (en4, /en4) vcc vcc 250r vcc 15k 15k 5k 5k 110r
zl40510/14 data sheet 26 zarlink semiconductor inc. 8.0 timing waveforms applying logic levels to the inputs, as shown in t able 1, gives the output wa veform shown in figure 26. pwr_up en2 en3 en4 output 0 x x x off 1 0 0 0 read 1 1 0 0 level 2 1 1 1 0 level 3 1 1 1 1 level 4 note: 1 = logic high, 0 = logic low and x = "don?t care" table 1 - output function for set logic inputs
zl40510/14 data sheet 27 zarlink semiconductor inc. 9.0 timing diagrams figure 25 - timing of read or write channels figure 26 - output waveform showing addition of read and write levels en(n) /en(n) t_on_ch t_off_ch iout=iin(n)*gain iout=0 pwr_up 50% en3 en4 off read level 2 level 4 ton_pwr_up ton2 ton3 toff3 toff2 toff_pwr_up toff4 ton4 en2 level 3
zl40510/14 data sheet 28 zarlink semiconductor inc. 10.0 example waveforms 10.1 write waveform the write output waveform may be produced as shown in example 1, figure 27. the erase level is set by switching off both the bias level and the write level. the write swit ching waveform is produced by switching off the erase level and switching on the bias level and then modulating that with the write level. the peak of the write waveform is the sum of the bias and the write levels. figure 27 - example of write waveform notes: 1. only the write signal changes to modulate the output during the write pulse. 2. each of the write channels can provide up to 500 ma. it is not necessary to add together the output of more than one write channel to achieve 500 ma. 10.2 oscillator waveform the oscillator may be enabled independently and is summed with the selected level. figure 28 - example of oscillator waveform superimposed on the read waveform note: the amplitude of the oscillator must be less than the programmed dc output level to avoid clipping and subsequent increase in harmonic distortion. write erase bias output bias erase write input erase write pwr_up 50% off read osc_ton osc_toff osc_en

www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of prod uct or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any pu rpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to pe rform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl, the zarlink semiconductor logo and the legerity logo and combinations thereof, voiceedge, voiceport, slac, islic, islac and voicepath are trademarks of zarlink semiconductor inc. technical documentation - not for resale for more information ab out all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of ZL40510LDG

	To Download ZL40510LDG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .